I. Field of the Disclosure
The technology of the present application relates generally to cell-based designs and circuits incorporating use of lower threshold voltage (Vt) (“Lvt”) devices and related methodologies to increase performance and reduce power consumption in a circuit.
II. Background
Semiconductor technology has evolved into using deep sub-micron geometries. Deep sub-micron geometries are generally those less than one-hundred (100) nanometers. Using deep sub-micron semiconductor devices (also called “sub-micron devices”) allows integration of more complex functionality into a smaller area. For example, sub-micron device technologies are used to produce complex system-on-a-chip (SOC) designs where size constraints are limiting. SOC designs may be used in portable devices, including but not limited to cellular phones, personal digital assistants (PDAs), laptop computers, other electronic devices, and the like, where size constraints are limiting.
Use of sub-micron devices is also advantageous because their smaller transistor channel lengths allow smaller cell areas and provide faster switching times. Faster switching times provide increased performance or speed. However, use of sub-micron devices comes with a tradeoff. Because of smaller transistor channel lengths in sub-micron devices, current continues to flow even during standby (i.e., non-switching) states due to “sub-threshold conduction.” Sub-threshold conduction leads to current leakage. When a gate-to-source voltage (Vgs) of a sub-micron gate is lower than its threshold voltage (Vt), it is in the sub-threshold region. The drain current reduces logarithmically with a reduction in Vgs until the device is completely turned off, such as in a standby state (i.e., Vgs=0). Semiconductor devices above sub-micron levels have higher Vts such that drain current is insignificant when the device is not activated or in a standby state. However, when Vt is lowered, as is the case in sub-micron devices, drain current becomes significant even when the device is not activated or in a standby state. Significant drain current results in significant leakage current and increased total power consumption since total power consumption is comprised of standby power consumption and active power consumption. Leakage current in sub-micron devices can be further exacerbated by use of very thin gate oxides in sub-micron devices. This may be of particular concern when employing sub-micron devices in portable devices or other devices that use battery power. Increased power consumption results in quicker battery drain and shorter battery life. Thus, increased power consumption due to leakage must be taken into consideration along with increased circuit performance when employing sub-micron devices.
To counter the issue of increased power consumption due to leakage current in sub-micron devices, manufacturers have created sub-micron devices with higher Vts. For example, higher Vt (Hvt) devices exhibit lower current leakage over lower Vt (Lvt) devices. For example, Hvt devices may exhibit sub-threshold leakage currents of approximately 1.0 nanoAmperes per micrometer (nA/μm). Lvt devices may exhibit sub-threshold leakage currents of approximately 10.0 nanoAmperes per micrometer (nA/μm), approximately ten times more than Hvt devices. However, circuit performance can be adversely affected by use of Hvt devices. Hvt devices have slower switching times than Lvt devices, but have lower leakage current as compared to nominal Vt (Nvt) devices. Lvt devices have faster switching times than Hvt devices, but higher leakage current as compared to Nvt devices.
To address the need for both increased performance and reduced power consumption that typically cannot be achieved by sole use of either Lvt devices or Hvt devices, circuits can be designed to employ mixed use of Lvt and Hvt devices. Lvt devices can be used in one or more critical speed paths to achieve desired performance. However, use of the Lvt devices increases power consumption of the circuit during standby modes due to sub-threshold conduction. To reduce power consumption during standby modes without affecting circuit performance, the non-critical speed paths can employ Hvt devices. However, even with the use of Lvt devices only in the critical paths of a circuit, standby power consumption may still be unacceptable. Replacing the Lvt devices with Hvt devices may not be possible without violating a minimum desired circuit performance.